Improving Fmax of FPGA circuits employing DPR to recover from configuration memory upsets

Field-Programmable Gate Arrays (FPGAs) provide an ideal platform for meeting the performance, cost and flexibility requirements of on-board processing in spacebourne applications. However, given the reliance on SRAM-based configuration memory, off-the-shelf FPGAs are vulnerable to radiation-induced Single Event Upsets (SEUs). The detection and mitigation of the effects of SEUs is therefore of paramount importance. Moreover, in time critical applications, it is also desirable to detect and recover from errors rapidly. Techniques for partially reconfiguring a corrupted module of a Triple Modular Redundant (TMR) implementation have been described in the literature. In this paper we address the speed penalty incurred with such techniques and provide a generalized approach for alleviating it. The results indicate that the speed penalty can be greatly reduced enabling rapid recovery from SEUs in reconfigurable hardware. Keywords—fault tolerance; radiation induced errors; reconfigurable hardware;